1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a manufacturing method of the array substrate for the liquid crystal display device.
2. Discussion of the Related Art
Generally, a liquid crystal display device includes a lower substrate, commonly referred to as an array substrate, that includes a thin film transistor, and an upper substrate, commonly referred to as a color filter substrate, that includes a color filter, and a liquid crystal material interposed between the upper substrate and the lower substrate. The liquid crystal display device makes use of optical anisotropy and polarization properties of the liquid crystal material to display images. Presently, active matrix LCD (AM LCD) devices are one of the most popular means for displaying images because of their high resolution and superiority in displaying moving images.
FIG. 1 is a cross-sectional view of a liquid crystal panel according to the related art. In FIG. 1, a liquid crystal panel 20 includes an upper substrate 4 and a lower substrate 2. The upper substrate 4 and the lower substrate 2 are spaced apart from each other with a liquid crystal material layer 10 interposed therebetween. The upper substrate 4 includes a color filter 8 to display color images, and the lower substrate 2 includes a switching element to change an alignment orientation of liquid crystal molecules of the liquid crystal material layer 10. The upper substrate 4 includes a black matrix 9 that is formed beneath a transparent substrate 1 to intercept light in a region other than a pixel region P. A color filter 8, which has sub-color-filters red (R), green (G), and blue (B) in a repetitious order, is formed under the black matrix 9 to display color images by transmitting only the light of particular wavelength range. A common electrode 12 is formed beneath the color filter 8 to apply a voltage to the liquid crystal material layer 10. A switching element, thin film transistor “T,” is formed on a transparent substrate 1 of the lower substrate 2. A pixel electrode 14, which receives a signal from the thin film transistor “T” and applies a voltage to the liquid crystal material layer 10, is formed on the lower substrate 2 within the pixel region P. An alignment layer (not shown) is formed on interior surfaces of the common and pixel electrodes 12 and 14 to align the liquid crystal molecules along a uniform direction.
FIG. 2 is a flow chart showing a photolithographic masking process for a liquid crystal display device according to the related art. The photolithographic masking process uses a photoresist material that undergoes a chemical reaction when exposed to light. Specifically, the photoresist material is coated on a substrate, and then a desired photoresist pattern is obtained by irradiating light onto the coated photoresist material layer using a mask. The mask includes a plurality of light block portions and a plurality of light transmission portions. The photoresist material can be classified into two types: a positive photoresist material and a negative photoresist material. When the positive photoresist material is used, a portion of the photoresist material that is exposed to light is removed during a subsequent development process. The positive photoresist material is commonly used for forming the black matrix and array elements, and the negative photoresist material is commonly used for patterning the color filter.
In FIG. 2, the photolithographic masking process includes a first step ST1 that is a photoresist coating process. During the first step ST1, a spin coating method is used to form a flat and uniform photoresist layer. During a second step ST2, a soft baking process for hardening the coated photoresist is performed. A third step ST3, includes a exposure process. During the third step ST3, the mask, which has mask patterns on a transparent substrate, is positioned over the coated photoresist material layer, and the coated photoresist material layer is exposed to light of a masking and exposure apparatus. A fourth step ST4 includes a development process. During the fourth step ST4, a particular portion of the photoresist layer is removed using a developer. During a fifth step ST5, a hard baking process is performed for improving a contact property between the coated photoresist material layer and a corresponding underlayer.
During the third step ST3, since the light exposure is performed in a way to transcribe a desired pattern onto the photoresist material layer using the masking and exposure apparatus that uses lens and mirrors to direct the light, a pattern distortion phenomenon, which is caused by the lens and mirrors of the light exposing apparatus, cannot be accurately controlled. For example, if a first pattern is distorted and a second pattern is to be formed on the basis of the first pattern, then the second pattern may be formed in a region displaced from a desired point. Accordingly, an overlay accuracy between the first and second patterns is decreased, and corresponding overlay differences increase as a number of subsequent processes are added. Moreover, if the overlay differences between the pixel region and an adjacent line increases, display quality of the images decreases.
FIG. 3 is a plan view illustrating a partial array substrate of a liquid crystal display device according to the related art. In FIG. 3, a horizontal gate line 32, which includes a gate electrode 30 and a capacitor electrode 31, is formed on an array substrate. A vertical data line 44, which includes a source electrode 40, crosses the gate line 32, thereby defining a pixel region. A drain electrode 42 is spaced apart from the source electrode 40. The gate electrode 30, the source electrode 40, and the drain electrode 42 constitute a thin film transistor T. A pixel electrode 50, which is connected to the thin film transistor T, is formed in the pixel region. The gate line 32 applies a scan signal to the pixel electrode 50, and the data line 44 applies a data signal to the pixel electrode 50. There may exist a parasitic capacitance, i.e., a coupling capacitance, between the data line 44 and an adjacent pixel electrode 50. Accordingly, if the parasitic capacitance value is different in each pixel region, then a deterioration of displayed images, such as a spot on the screen, may occur. The capacitance can be expressed numerically as follows:C=∈(A/d)  (1)where “C” is a capacitance, “∈” is a dielectric constant of insulator, “A” is an area of an electrode and “d” is a distance between electrodes. Accordingly, since a distance between the data line 44 and the pixel electrode 50 affects the coupling capacitance value, it is necessary to maintain a uniform distance between the data line 44 and the pixel electrode 50 to maintain the quality of the displayed images.
FIGS. 4A to 4C are cross-sectional views taken along A—A, B—B of FIG. 3, and illustrating a fabrication process for an array substrate according to the related art.
In FIG. 4A, a thin film transistor “T” and a data line 44 are formed on a transparent substrate 1. A gate electrode 30 is formed on the transparent substrate 1, and a gate insulating layer 34 is formed on the gate electrode 30 and on the substrate 1. An active layer 36a is formed by depositing amorphous silicon (a-Si) on the gate insulating layer 34, and an ohmic contact layer 36b is formed by depositing doped amorphous silicon on the active layer 36a. The active layer 36a and the ohmic contact layer 36b constitute a semiconductor layer 36. A source electrode 40 and a drain electrode 42, which is spaced apart from the source electrode 40, are formed on the semiconductor layer 36. A channel ch is formed between the source electrode 40 and the drain electrode 42 by removing a portion of the ohmic contact layer 36b between the source electrode 40 and the drain electrode 42, thereby exposing the active layer 36a between the source electrode 40 and the drain electrode 42. The gate electrode 30, the semiconductor layer 36, the source electrode 40, the drain electrode 42 and the channel ch constitute the thin film transistor T. The data line 44 is formed simultaneously with a forming process of the source electrode 40 and the drain electrode 42.
In FIG. 4B, a passivation layer 46 is formed on the thin film transistor T and on the data line 44 to protect the thin film transistor T. A drain contact hole 48 is formed through the passivation layer 46 to expose a portion of the drain electrode 42.
In FIG. 4C, pixel electrodes 50, which include a transparent conductive material, are formed on the passivation layer 46. The pixel electrodes 50 contact the corresponding drain electrodes 42 through the drain contact holes 48. The pixel electrodes 50 are uniformly positioned on both sides of the data line 44 by a distance “a” between the data line 44 and the pixel electrode 50 on the left side, and a distance “b” between the data line 44 and the pixel electrode 50 on the right side. However, during the photolithographic masking process, pattern distortion occurs.
FIG. 5 is a cross-sectional view illustrating an array substrate for a liquid crystal display device according to the related art. In FIG. 5, since a distance “a” between the data line 52 and the pixel electrode 54 on the left side is smaller than a distance “b” between the data line 52 and the pixel electrode 54 on the right side, the coupling capacitance of each region between the data line 52 and the pixel electrode 54 is different, whereby a voltage that is applied to each pixel electrode is different. Accordingly, if the voltage applied to each pixel is different, an alignment orientation of the liquid crystal material cannot be uniformly controlled. Thus, the quality of the displayed images deteriorates. Moreover, since a rework of the photolithographic masking process is necessary to prevent deterioration of the displayed images, processing time increases and production yields decrease.